Semiconductor devices, for example Zener diodes, are well known in the art. However, for a number of reasons, the manufacturing yield and reliability of semiconductor devices is less than optimal. For example, the existence of defects in the masks and masking layers used to fabricate the various doped regions making up the device can produce unwanted holes or weak spots in the protective surface dielectric or mask and lead to low resistance shunts across the PN junction when the holes or weak spots are filled or decorated with metal during contact metallization. This leads to a higher than desired incidence of shorts or premature breakdown and, therefore, lower than expected manufacturing yield.
Another problem is the existence of edge defects which can alter the electronic properties of the semiconductor substrate in which the devices are fabricated. Semiconductor devices are fabricated in wafer form and the wafers are then cut into many individual die by scribing or sawing or a combination thereof. Scribing for example, may be by a scribing tool or by a laser. Sawing for example, may be by one or more diamond coated sawing wheels or one or more wire saws which are wet with an abrasive slurry, or a combination thereof. All of these methods produce to varying degrees, crystalline defects in the edge of the die. The electrical effect of such edge defects can extend for a substantial distance into the die and alter the electrical properties of PN junctions or other active regions within the die.
There is an ongoing desire to make device die smaller so that a greater number can be obtained from each wafer. One way of doing this is to reduce the separation between the active regions of the device and the scribe or saw grid at the die periphery. However, as this distance is decreased the adverse influence of edge defects is increased with the result that the manufacturing yield can decline even though there are more die available per wafer. Propagation of such edge cracks into the die as a result of temperature cycling can shorten the useful life of the semiconductor device.
Another problem is created by surface defects, that is, defects in the major surface of the wafer in which the diode, transistor or other semiconductor device is formed. Some of these defects are present in the starting wafer and some are created during wafer processing. If there are surface defects in proximity to critical PN junctions or other active device regions, then device performance and reliability can be adversely affected. Propagation of such surface defects into the die as a result of temperature cycling can shorten the useful life of the semiconductor device.
A number of attempts have been made in the prior art to avoid these and other problems associated with semiconductor devices and semiconductor device manufacture. For example, use of a deep diffused .pi.-ring to achieve high breakdown voltage diodes is described by Georgescu et al. ("Planar Termination for High-voltage P-N Junctions", Solid-State Electronics, Vol., 29, No. 10, 1035-1039, 1986). Ahmad et al ("A Proposed Planar Junction Structure With Near-Ideal Breakdown Characteristics", IEEE Electron Devices Letters, Vol. EDL6, No. 9, Pages 465 ff, September 1985), describe the use of a low concentration P-type pocket around the edge region of a P+N type junction to improve the electric field distribution and give near ideal high voltage breakdown characteristics in diodes. Adler et al. ("Breakdown Voltage for Planar Devices with a Single Field Limiting Ring", PESC 75 Record, pages 300-313), Brieger et al. ("Blocking Capability of Planar Devices with Field Limiting Rings", Solid State Electronics, Vol. 26, No. 8, pages 739-745, 1983), Kao et al. ("High-voltage Planar PN Junctions", Proceedings of the IEEE, Vol. 55, No. 8, page 1409 ff, August 1967), and Herman et al. (U.S. Pat. Nos. 4,399, 499 and 4,412,242) describe, among other things, use of one or more P.sup.+ rings around a P.sup.+ N junction to achieve high breakdown voltage. Jaecklin et al. (U.S. Pat. No. 4,305,085) use a combination of P and N.sup.+ guards rings around a PN junction to improve the reverse current behavior of the junctions. Ghandi ("Semiconductor Power Devices", John Wiley and Sons, NY, page 63 ff, 1977), teaches the use of one or more diffused guard ring structures to control field spreading and achieve high voltage diode breakdown. Temple ("Increased Avalanche Breakdown Voltage and Controlled Surface Electric Fields Using a Junction Termination Extension (JTE) Technique", IEEE Transactions on Electron Devices, vol. ED-30, No. 8, pages 954-957, August 1983), describes use of ion implantation around the main PN junction to control the field distribution and achieve high breakdown voltages. Valdmann describes planar avalanche diode with low breakdown voltage (4-8 volts) using a P-type guard ring around a central PN junction of reduced depth compared to the guard ring in U.S. Pat. No. 4,323,909. Zwernemann describes a high voltage Schottky rectifier employing a diffused guard ring in U.S. Pat. Nos. 3,821,772 and 3,907,617. The above-noted patents are incorporated herein by reference.
Despite the large amount of work that has gone into obtaining PN junctions of improved properties and semiconductor devices with improved reliability and yield, many of the above-described problems remain. Thus, there is an on-going need for improved structures and fabrication techniques which avoid long standing problems associated with prior art semiconductor and manufacturing techniques, especially with junctions intended to function as Zener diodes.
As used herein, the words "Zener diode" (singular or plural) are intended to refer to all kinds of PN junctions exhibiting voltage reference behavior, whether or not the breakdown phenomena is of Zener, avalanche, punch-through or other type. Also, as used herein, the words "scribe" and "scribing" are intended to refer collectively to any or all means for separating a wafer into individual die, regardless of whether that is accomplished by sawing, scribing, breaking, a combination of the foregoing or otherwise. The words "scribe grid" are intended to refer to the region on a semiconductor wafer at the periphery of individual semiconductor die where scribing is intended to be performed. As used herein the words "metal" and "metallization" are intended to refer to metals, semimetals, heavily doped polycrystalline semiconductors or combinations thereof applied to single crystal semiconductors for the purpose making contact thereto.
As used herein, the words "lateral" and laterally" are intended to refer to directions parallel to the principal surface of the semiconductor wafer or die being discussed and the words "vertical" and "vertically" are intended to refer to directions substantially perpendicular thereto.
The notation (a)E(b) is used to express numbers in scientific notation with the base ten, where (a) is the value and (b) is the power of ten by which the value is multiplied to obtain the number, for example, 5E6=5.times.10.sup.6 =5,000,000. This notation is well understood in the art.